product

Satellite - DVB-S2 demodulator

  • Product
  • IP Core Products
  • Satellite
  • DVB-S2 demodulator

Product code: CMS0014

The CMS0014 has been designed from the ground-up for high-speed and gate-efficient implementation on FPGA and ASIC platforms and offers "near Shannon limit" performance when combined with an advanced LDPC decoder solution such as TurboConcept's TC4000.

The demodulator provides an adaptable starting point for receiver sub-systems to be used in the next-generation of digital TV set-top-boxes, VSAT terminals and related test and monitoring equipment.

Also see

- DVB-S2 modulator - TurboConcept TC4000 LDPC decoder

Block diagram

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Safari Plug-in

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Release note

Download

Technical data brief

8th May 2007 (296 kB)

IP Guide

6th November 2008 (566 kB)

Altera megacore

v0.5.3 (11.39 MB)

Certification

Standards compliance

ETSI EN 302 307

Features

Support for CCM, VCM and ACM modes.

Sync acquisition at -2dB C/N.

Wide carrier acquisition range.

Programmable symbol rate recovery.

few kSymb/s to >45 MSymb/s.

Real IF, zero-IF or near-zero-IF.

Variable ADC sampling frequency.

Frame-by-frame (A)PSK selection.

QPSK, 8PSK, 16APSK, 32APSK.

Short (16kb) and normal (64kb) frames.

Frames with/without intra-frame Pilots.

Applications

ASICs for digital satellite TV reception.

High-end interactive satellite terminals.

Test, measurement and broadcast monitoring equipment.

Multi-standard, adaptable (software defined) receivers.

Implementation

Single external clock source.

Single external analogue AGC loop.

All-digital timing and carrier recovery.

Digital channel filtering.

Optimised for ASIC, Xilinx and Altera.

Verified with the TC4000 LDPC decoder.

Evaluation boards available.

Plug-ins / Extensions

Group-delay equalisation.